Conventionally, technology has been disclosed that records, as a history of simulation results, “the number of times failure occurs” and “information related to the time at which failure occurs” to identify assertions that have failed and assertions that are valid. Further, technology has been disclosed that when an error occurs during simulation, analyzes with which test pattern the error occurred and displays the pattern. For examples, refer to Japanese Laid-Open Patent Publication Nos. 2008-158696 and 2002-149440.
If the verification engineer does not sufficiently understand or misunderstands the specifications from which the assertions are created, the created assertions may include errors. If such an assertion is used to simulate a circuit-under-test and the assertion fails, it cannot be determined whether the assertion is correct and failed or whether the assertion includes an error and consequently failed. Further, simulation results due to failure appear in many ways depending on the contents of the assertion.
Therefore, the verification engineer again analyzes the specifications, or the verification engineer and the design engineer again confirm the specifications, and then the assertions have to be corrected. As a result, a problem arises in that correction work for the assertions is time consuming.
Further, with the technology above, since processing is performed under the assumption that the assertions are correct, a problem arises in that assertion errors based on insufficient understanding or a misunderstanding of the specifications are difficult to identify.